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katkoori s behavioral synthesis hardware security 2022

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Textbook in PDF format This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Today, behavioral synthesis tools are widely used in industry to routinely design billion-transistor complex integrated circuits. While there are several knobs available in these tools for area, power, and performance optimization, none exist for automatically incorporating security in a design. The primary reason for this state of affairs is that the problem of hardware security is not yet well understood. The problem inherently is a difficult problem, for example, there is no metric to measure the level of security, unlike those available for area, power, and performance. There is a large and active community of hardware security researchers addressing the secure design problem at lower levels of design abstraction, namely at physical and gate levels. Relatively speaking, the number of research groups working at higher levels of abstractions is low. The main reason is that the knowledge base built at the lower levels is quintessential to address the problem reliably at the higher levels (as was the case with the area, power, and performance optimization). This edited book provides a snapshot of the ongoing hardware security research at the register-transfer level and above. The intended audience are the academic researchers actively conducting research in the area as well as those who intend to work in this area. Further, the designers in the semiconductor industry can benefit by understanding how one could address the problem at higher levels. The book can also be used in undergraduate or graduate advanced hardware security elective. Provides a single-source reference to behavioral synthesis for hardware security; Describes automatic synthesis techniques for algorithmic obfuscation, using code transformations; Includes behavioral synthesis techniques for intellectual property protection. Introduction and Background Hardware IP Protection Through Obfuscation Behavioral Synthesis of Key-Obfuscated RTL IP Source Code Obfuscation of Behavioral IPs: Challenges and Solutions Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud Protecting Hardware IP Cores During High-Level Synthesis Hardware IP Protection Through Watermarking and State Encoding Hardware (IP) Watermarking During Behavioral Synthesis Encoding of Finite-State Controllers for Graded Security and Power State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm Hardware Trojan: Modeling, Localization, and Defense Hardware Trojan Localization: Modeling and Empirical Approach Defense Against Hardware Trojan Collusion in MPSoCs A Framework for Detecting Hardware Trojans in RTL Using Artificial Immune Systems Side-Channel Defense via Behavioral Synthesis High-Level Synthesis for Minimizing Power Side-Channel Information Leakage S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits Integrating Information Flow Tracking into High-Level Synthesis Design Flow

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Katkoori S. Behavioral Synthesis for Hardware Security 2022.pdf 12.3 MB

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katkoori s behavioral synthesis hardware security 2022