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furey d delay insensitive circuits structures semantics strategies 2023

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Textbook in PDF format Delay insensitive circuits rely on local coordination and control from the ground up, enabling data and signal processing applications without any clock distribution network whatsoever. This ability can bring a welcome relief to projects whose timing infrastructure would otherwise tend to create more problems than it solves. The quest for performant, robust electronics for data and signal processing applications has often depended on the help of a small close-knit faction of specialists in asynchronous circuit design working on the margins of the broader engineering community. On those rare but dreaded occasions when its technical debt comes due, the deeply held assumption of discrete global time in synchronous design (as opposed to asynchronous design) harshly reaffirms the need for their esoteric skills. Sometimes incremental progress is achievable by a combination of synchronous and asynchronous circuitry carefully organized as far as possible to insulate the majority of engineers from unwelcome contingencies. For example, when following the Globally Asynchronous Locally Synchronous (GALS) methodology, the mainly synchronous designer proceeds more warily but otherwise the same as usual for circuits up to a certain size and complexity, and defers reluctantly to asynchronous interface techniques only at the point where the liabilities of synchronous design become impossible to ignore (due to heat dissipation, clock skew, power consumption, metastability, electromagnetic interference, or the prohibitive cost and performance penalties of a global clock distribution network). The ingenuity of the GALS methodology as a response to a given regime of cultural and business constraints can only be admired, but it invites speculation about the greater things that could be achieved if the asynchronous designer were allowed a freer hand. A notable effort in this direction was the investigation of so called Delay Insensitive (DI) circuits, pioneered mainly during the 1990s. A style of circuits designed from the ground up for asynchronous operation and scalable to any size, they were seen to lend themselves to a tightly cohesive theoretical framework enabling a full complement of rigorously well founded synthesis and verification tools. Among the most promising implications were fewer bugs, less tedium for the designer, lower power consumption, and mechanically checkable semantics-preserving optimization. Field Programmable Gate Arrays (FPGA) would seem ideally situated to attract similar interest, but have achieved only limited success in that regard at best. Although undoubtedly due in part to the marketing focus on commercial developers by the major FPGA vendors, this unfortunate circumstance might be more aptly explained by the hard truth that FPGA programming is a little too much like work to fit most people’s idea of a recreational activity. The true hacker’s satisfaction derives from seeing the emergent properties of the brainchild take on a life of their own. By contrast, a system that must be dragged, cajoled, prodded, and kicked, only to yield a less interesting return than the sum of the effort expended, lacks this essential allure. The current state of FPGA technology relegates the bulk of the developer’s working life to an endless routine of troubleshooting problems with timing. A correct and complete design with respect to the semantics of the specification language is only the beginning of the real work. The aim of this book is to present a curated study of one possible route to the topic of delay insensitivity. While the treatment is meant to be accessible to non-specialists, the level of detail is pitched to enable a sufficiently motivated reader to replicate any of the techniques discussed. Whether a spectator or participant, the ideal reader is envisioned as an inpert: the opposite of an expert, self-directed with an eye on the future, not unduly constrained by preconceptions, nor lacking in skepticism, but willing to forgive an occasional departure from convention in the service of a worthy cause. Prior knowledge of digital circuit design is not required and could well be a hindrance, but a basic college undergraduate-level or auto-didactic acquaintance with discrete math is assumed (e.g., functions, sets, relations, graphs, state machines etc., and maybe a splash of probability theory for just one chapter). Readers wishing to dig more deeply should find enough material in the bibliography to keep them busy. Where possible, freely available books, dissertations, technical reports, and draft articles are cited in preference to their paywalled equivalents. Rather, this book calls for being read in the spirit in which it was written, as an idle diversion for a bored student, engineer, entrepreneur, academic researcher, or maybe even a forward thinking manager given to wondering whether our current working practices are really the best we can do

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furey d delay insensitive circuits structures semantics strategies 2023

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