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geerts y design multi bit delta sigma ad conversters 2002

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Textbook in PDF format Over the last decade, a vast evolution of communication systems was observed. The enormous popularity and expansion of the internet was a driving force for the development of broadband internet access in every home to cope with the increasing bandwidth requirements for multimedia applications. At the same time, wireless communication evolved from an analog network with large devices, to small and cheap handsets which are based on digital communication standards. The core of all these complex electronic systems consists of digital circuits which have a huge computational power and are implemented in CMOS technologies. The development of ever faster and more powerful digital cores opens the way to more complex systems with increasing demands for the analog part which has to provide an interfacing layer to the outside world. One of the crucial building blocks in the analog part is the Analog to Digital converter. The goal of this work is to present an architecture study of AD converters and to provide insight into a wide range of analog circuit imperfections which can limit the performance. The emphasis is put on high-speed high-resolution converters in CMOS, although the material can also be applied for other specification goals and technologies. The first part of this work takes a closer look at various architectures of AD converters. These range from single-loop to cascaded and various multi-bit topologies. The operation and several stability issues of the converters are discussed. The various topologies are optimized to obtain stable converters with a high accuracy and a clear overview is provided of the maximum achievable performance of each topology. Finally, the linearity problem of the DA converter in the feedback loop of multi-bit converters is discussed, together with possible solutions. The second part studies several design aspects of converters, with a special focus on multi-bit implementations. Various models are provided for a wide range of linear and non-linear circuit non-idealities which can degrade the performance of the converter. These models allow the designer to determine the required specifications for the different building blocks. A power estimation is presented and used to derive several design considerations. The last part discusses the systematic design and measurement results of two implementations. The first is a cascaded 2-1-1 converter, implemented in a 3.3V 0.5um standard CMOS technology. It achieves a dynamic range of 92dB for a Nyquist-rate of 2.2MHz. The second converter is a multi-bit third-order topology with Dynamic Element Matching to relax the linearity requirements for the DAC. It is implemented in a standard 0.65um CMOS technology, achieves a dynamic range of 97dB and a Nyquist-rate of 2.5MHz

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Geerts Y. Design of Multi-bit Delta-Sigma AD Conversters 2002.pdf 30.9 MB

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geerts y design multi bit delta sigma ad conversters 2002